RTL Design for CPU Sub-Systems

Join Cypress Semiconductor’s IoT  Team and develop System on Chip. This team is searching for a hands-on, team-oriented design engineers with a proven track record.

In this role, the engineer will be responsible for developing CPU Sub System. We are looking for self-motivated and experienced engineers who can work with minimal supervision in our design team and be able to work closely with our local and global design teams

We are Hiring! RTL Design Engineers for # IOT SoCs

Job description: Develop a multi-core ARM CPU subsystem with following responsibilities:

  1. Contribute to the closure of design specification.
  2. Arrive architecture/micro-architecture.
  3. Optimized RTL design using VHDL/Verilog.
  4. Integration of third-party IPs with AMBA & proprietary interconnects.
  5. Involve in IP/subsystem level verification, emulation platform development and lab debugging. Participate in synthesis, static timing analysis, DFT, post-silicon validation and debug.

Requirement:  5+ Years of ASIC/SOC RTL Design Experience with following skills. 

  1. Good exposure to latest ARM CPU/processor architecture. 
  2. Proficient in micro-architecture and Verilog/VHDL coding.
  3. low power design concepts. 
  4. Strong skills in front-end flows like lint, CDC, and LEC
  5. Bus protocols like AMBA AXI/AHB,APB, cache protocols, coherency. 
  6. Experience in C/C++ & assembly coding, CPF/UPF Flow
  7. Strong skills in scripting: TCL, Perl, Python etc.

Job Location: Bangalore, India

If you think this is exciting and you are interested to explore. please send me your latest resume to Jayant.Joshi@Cypress.com

Thanks & Regards,
Jayant

CPU SS RTL Design

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Design Automation Engr : Tools, flow, Methodology

Looking for a problem solver with a keen eye to detect and solve flow effectiveness and efficiency challenges in RTL2GDS flow. Your work will impact all design platforms used in Cypress worldwide.

Its an opportunity to grow as the methodology owner of multiple areas of design flow and provide complete CAD solution to design teams – including anticipating/understanding future needs, enabling them to create “World’s best Semiconductor – on-time, every time”.

Own RTL2GDS flow used in Cypress – evaluate and deploy required tools & flow and close methodology gaps using automation and tool development.

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Required Skills:

  • Need to understand basic devices and RTL coding, understand overall RTL2GDS flow, with expertise in one of DFT, PnR or STA.
  • Person must be good in aptitude, debugging and automation, SW Development
  • Experience: 4 to 10 Years of Industry experience

Immediate responsibility:

  • Run CAD projects – plan and drive ongoing projects to meet existing design requirements.
  • Work involves the evaluation, integration, and training required for new and improved tools and changes to the design methodology. This includes interaction with design and the associated time to market/speed/area trade-offs.
  • Will be responsible for understanding design methods and current gaps, tool/methodology evaluation/deployment, support deployed tools and driving methodology for productive design environment.
  • Understand and define design methodologies across semicustom design flow  (RTL analysis, Synthesis, Place and route, STA, extraction, dynamic IR, physical verification).
  • Must be able to identify methodology gaps and improvements and provide automation to perform all design activities in the most efficient and correct by construction way.

If you think this is exciting and you are interested to explore. please send me your latest resume to Jayant.Joshi@Cypress.com

Thanks & Regards,
Jayant

Cypress Semiconductor

TO ALL RECRUITMENT AGENCIES:

Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.

Ireland: Analog Design Engineer

Cypress Semiconductor Ireland is the Centre of Excellence for Capacitive Sensing IP development within Cypress Semiconductor.

The team is developing product differentiating Human-Machine-Interface IP for several markets including Automotive, Home Appliance and Internet of Things/Wearables. The team is responsible for the design and development of capacitive sensing IP such as Touch Screen Controllers, Fingerprint Controllers and Capacitive Sensing Controllers.

We are actively seeking talented IC engineers who want to join a dynamic and experienced team and take their technical knowledge to the next level in our mission of excellence.

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Please go through the job description:

Cypress Semiconductor Ireland is recruiting an analog circuit designer to join its team in Cork, Ireland. 

We seek Analog & Mixed signal designers with good knowledge of analog circuits achieving high performance, low power, and efficient implementation

Desired skills 

Strong knowledge of analog design fundamentals, experience with OPUS design entry, HDL design entry, circuit simulation, mixed signal simulation and modeling.

Minimum Education & Work Experience: BSEE required, MSEE preferred; relevant project experience.

Good problem solving and communication skills. Team player.

Degree & Discipline: ME, MICROELECTRONICS & EMBEDDED SYSTEMS
Experience in Industry: 2-5 years.

PS: If you are not an Ireland Citizen, Request you to share your valid work permit details to work in which will help me process your resume/application forward.

If you think this is exciting and you are interested to explore. please send me your latest resume to Jayant.Joshi@Cypress.com

Thanks & Regards,
Jayant

Cypress Semiconductor

TO ALL RECRUITMENT AGENCIES:

Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.

 

Germany: Digital Design Engineer

Join our design team for digital video and graphics IP in Munich, Germany and contribute to the development of mission critical components for our Automotive and Industrial MCU products. We are looking for a digital design expert with focus on architecture definition and conceptual pre-development topics.

Skills Required: 

Deep knowledge in digital hardware design, MCU architectures and video processing techniques. Strong professional background in logic IP development on module and subsystem level. Preferable with experience in verification (UVM) and virtual prototyping (TLM)

Key Words: digital design, verification, architecture, concept, system, video, graphics, prototyping

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We are looking for an experienced candidate with focus on architecture work: interfacing between system architects / marketing and the design team, owning the architecture specification for subsystem level components.

Beside that focus, the candidate should have solid background in digital hardware design and all related development steps (verification, modelling, prototyping).

German language skills would be a big plus

Good problem solving and communication skills. Team player.

Degree & Discipline: ME, MICROELECTRONICS & EMBEDDED SYSTEMS
Experience in Industry: 4-8 years.

PS: If you are not an German citizen, request you to share your valid work permit details to work in which will help me process your resume/application forward.

If you think this is exciting and you are interested to explore. please send me your latest resume to Jayant.Joshi@Cypress.com

Thanks & Regards,
Jayant

TO ALL RECRUITMENT AGENCIES:

Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.

 

CPU Sub-System Design Verification

Join Cypress Semiconductor’s IoT  Team and develop System on Chip. This team is searching for a hands-on, team-oriented design engineers with a proven track record.

In this role, the engineer will be responsible for developing CPU Sub System. We are looking for self-motivated and experienced engineers who can work with minimal supervision in our design team and be able to work closely with our local and global design teams

Job description: Design Verification of ARM CPU subsystem with following responsibilities:

1.Functional/performance verification of ARM sub system

2.SoC platform verification with AMBA interconnect and ARM CPUs

3.Build up test bench and simulation environment

4.write test plan according to design

5.Meet verification metrics like functional/code/toggle coverages

6.CPF/UPF Simulations

Requirement:  5+ Years of  Design Verification Experience with following skills

1. Good exposure to latest ARM processor architecture

2.Strong ARM based SOC verification experience

3.Proficient in Verilog/VHDL & experience with C/C++ and assembly language

4.Familiarity with AMBA – AXI,AHB,APB protocols

5.Proficiency in SystemVerilog, SystemC, UVM, and/or VMM

6.Strong verification skills like test planning, debug

7.Assertion based verification” knowledge

8.Familiarity with UPF/CPF based Verification flow and GLS

9.Strong skills in scripting: TCL, Perl, Python etc

Job Location: Bangalore, India

If you think this is exciting and you are interested to explore. please send me your latest resume to Jayant.Joshi@Cypress.com

Thanks & Regards,
Jayant

CPU SS DV

RTL Design Engineers

Connecting “things” together to enhance convenience and intelligence in everyday life is what the Internet of Things (IoT) is all about. As the world’s leading supplier of connectivity solutions and flexible, ultra-low-power microcontrollers, Cypress is helping dreamers from startups to leading manufacturers bring their innovations to market quickly. By joining Cypress, you will become part of this exciting market opportunity.

Job Description:

  • This position is for WLAN PHY design of complex, low power SoCs targeted for IOT markets.
  • Design, development and verification in WLAN PHY
  • Create design documents
  • Implement optimized design using VHDL/Verilog/HLS
  • Develop and execute thorough simulation and verification plan including bit-matching with reference model
  • Participate in the emulation platform development and lab debugging
  • Participate in synthesis, static timing analysis, DFT
  • Participate in post-silicon validation and debug

Skills: 

  • Good knowledge of digital communication systems and low power, high speed digital data path design.
  • Strong analytical, and problem solving skills as well as hands-on debugging skills.
  • Good knowledge of RTL data path design and verification.
  • Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix Scripting, and C.
  • Experience with PHY design/implementation/verification of communication systems/protocols such as 802.11, LTE etc
  • Familiarity with HLS tools/flow is a plus
  • Self-motivated, excellent communication skills and ability to excel in a team environment
  • 5+ Years of Work experience is required.

Job Location: Bangalore, India

If you think this is exciting and you are interested to explore. please send me your latest resume to Jayant.Joshi@Cypress.com

Thanks & Regards,
Jayant

RTL

WiFi – Embedded Software

The Internet of Things is expected to grow to include more than 50 billion devices by 2020 – and Cypress’ out-of-the-box connectivity platforms are providing developers with the tools to kick-start their life-changing devices. As a leader in Wi-Fi, Bluetooth and Bluetooth Smart, Cypress ensures that standards-based connectivity technologies play nicely together, whether at home, in the office or on the go. With all of that embedded hardware engineering already complete, Cypress’ hardware and software development kits help to quickly turn creative IoT ideas quickly into prototypes and ready-for-market devices for both large and small companies.

Interoperability is critical to the proliferation of the Internet of Things, which is why the WICED™ platform is bringing secure Wi-Fi, Bluetooth and Bluetooth Low Energy (BLE) wireless connectivity to nearly every emerging product category in the Internet of Things ecosystem, including home appliances, health and fitness monitors, automation and asset tracking systems, smart meters and an array of consumer electronics devices.

WiFi Software.PNG

Job specific requirement:

  • Typically requires a BS in computer science or engineering plus a minimum of 6+ years of relevant software development experience, or an MS and 4+ year.
  • Strong Proficiency in C programming and experience in design/development of software in deeply embedded platforms
  • Strong knowledge and experience with ARM processors and RTOS such as ThreadX, FreeRTOS etc.
  • Must understand OS concepts of: threads and process, DMA engines, interrupt handling, timers, memory virtualization, IPC, race conditions etc
  • Working knowledge of TCP/IP based networking architecture and IoT protocols such as HTTP, CoAP, MQTT etc. is desired
  • Strong analytical, diagnostic and problem solving skills – Familiarity with embedded debugging tools and programming in a resource constrained environment.

Degree & Discipline: ME, MICROELECTRONICS & EMBEDDED SYSTEMS

Experience in Industry: 6-9 years

Job Location: Bangalore, India

If you think this is exciting and you are interested to explore. please send me your latest resume to Jayant.Joshi@Cypress.com

Thanks & Regards,

Jayant

STA – Staff / Sr Staff Engineer

Connecting “things” together to enhance convenience and intelligence in everyday life is what the Internet of Things (IoT) is all about. As the world’s leading supplier of connectivity solutions and flexible, ultra-low-power microcontrollers, Cypress is helping dreamers from startups to leading manufacturers bring their innovations to market quickly. By joining Cypress, you will become part of this exciting market opportunity.

We are hiring STA Engineers at Staff/Senior Staff level

STA

Job Description:

  1. B.E./B.Tech. with 7-9 years of experience or M.E./MTech. with 5-7 years of experience and specialization in VLSI design
  2. Strong hands-on technical experience in constraints development, timing analysis/closure of large SoCs
  3. Expert user of industry standard tools for timing signoff
  4. Experience in scripting languages (shell, perl, tcl) and Make flow.
  5. Understanding of 40nm/28nm technologies and associated timing/SI closure challenges
  6. Experience in low-power synthesis and equivalence checks will be a plus
  7. Must be well organized, methodical and detail oriented

Skills: 

  1. This position is for STA and Timing Closure of complex, low power SoCs targeted for IOT markets.
  2. Candidate will work on constraints development for functional/test modes at pre/post layout stage.
  3. Candidate will be responsible for timing analysis and convergence of large hierarchical designs.
  4. Candidate will work closely with the physical design team for timing/SI closure.
  5. Candidate is expected to have deep understanding of low power design techniques and experience in Multi-Mode-Multi-Corner timing analysis/closure

Job Location: Bangalore, India

If you think this is exciting and you are interested to explore. please send me your latest resume to Jayant.Joshi@Cypress.com

Thanks & Regards,
Jayant

Physical Design – Principal Engineer

Connecting “things” together to enhance convenience and intelligence in everyday life is what the Internet of Things (IoT) is all about. As the world’s leading supplier of connectivity solutions and flexible, ultra-low-power microcontrollers, Cypress is helping dreamers from startups to leading manufacturers bring their innovations to market quickly. By joining Cypress, you will become part of this exciting market opportunity.

We are hiring Physical Design Engineers at Principal Engineer

PD

Job Description:

  1. This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT markets.
    2. Candidate will work on various stages of physical design implementation which includes floor-planning, power grid design, place and route, clock tree synthesis, timing closure, physical verification checks.
    3. Candidate is expected to have a deep understanding of low power design techniques.
    4. Candidate will be responsible to achieve die area, performance, power goals for blocks/top.

Skills:

  1. B.E./B.Tech. with 12-13 years of experience or M.E./MTech. with 10-11 years of experience
  2. Hands-on experience in physical design and timing closure of large blocks/top
  3. Expert user of industry standard tools for physical design and signoff.
  4. Expert in scripting languages (shell, perl, tcl) and Make flow
  5. In-depth knowledge of 40nm/28nm technologies and associated physical design challenges
  6. Experience in low power checks will be a plus
  7. Should be self-motivated and take initiatives to drive new methodologies
  8. Should have strong written and verbal communication skills

Job Location: Bangalore, India

If you think this is exciting and you are interested to explore. please send me your latest resume to Jayant.Joshi@Cypress.com

Thanks & Regards,

Jayant

DFT Engineers

Connecting “things” together to enhance convenience and intelligence in everyday life is what the Internet of Things (IoT) is all about. As the world’s leading supplier of connectivity solutions and flexible, ultra-low-power microcontrollers, Cypress is helping dreamers from startups to leading manufacturers bring their innovations to market quickly. By joining Cypress, you will become part of this exciting market opportunity.

We are hiring DFT Engineers with 4 to 14 years of Experience

DFT

Job Description:  

  • This position is for DFT of complex, low power SoCs targeted for IOT markets.
  • Candidate will work on various stages of DFT implementation which includes Mbist implementation, scan implementation, DFT simulations and STA timing closure.
  • Candidate is expected to have deep understanding of DFT techniques and STA timing closure.
  • Candidate will be responsible to achieve best test quality and time with high yield
  • B.E./B. Tech. with 5-14 years of experience or M.E./MTech. with 3-13 years of experience and  specialization in VLSI design
  • Hands-on experience in DFT logic insertion, simulations and timing closure of large blocks/top
  • Expert user of Mentor/Logic vision DFT tools.
  • Expert in Silicon bring up and failure analysis.
  • Good at DFT low power architecture.
  • Expert in scripting languages (shell, perl, tcl) and Make flow
  • ATE hands on experience will be a plus
  • Should be self-motivated and take initiatives to drive new methodologies
  • Should have strong written and verbal communication skills

Job Location: Bangalore, India

If you think this is exciting and you are interested to explore. please send me your latest resume to Jayant.Joshi@Cypress.com

Thanks & Regards,

Jayant